ADCs may be used to convert a continuous analog signal into a discrete digital signal. One type of ADC is an SAR ADC. An SAR ADC uses an analog voltage comparator, a successive approximation register, and an internal digital-to-analog converter (DAC). In operation, an SAR ADC performs a binary search on each sample of the analog signal to determine an approximate digital output for each sample.
Charge distribution SAR ADCs are a common way of implementing SAR ADCs using an array of individually switched capacitor stages as the internal DAC. The array is used to perform the binary search using a comparator and a successive approximation register. Each capacitor stage has a binary-weighted capacitance and corresponds to a bit of the digital output. For example, if the most significant bit (MSB) capacitor stage has capacitance C, then the next most significant bit capacitor stages respectively have capacitances C/2, C/4, C/8, etc.
The capacitor stages may contain manufacturing defects so that the capacitance ratios between the capacitor stages may not match the above sequence of capacitance ratios, i.e. C, C/2, C/4, C/8, etc. These defects may cause the charge distribution SAR ADC to produce incorrect digital outputs in some cases and thus reduce the overall resolution of the SAR ADC. It may be necessary to calibrate the capacitor stages to correct for these defects and improve the accuracy of the SAR ADC. Both analog techniques and digital techniques exist for calibrating a charge distribution SAR ADC, but there are limitations to both types of approaches.
Analog calibration techniques may physically adjust the capacitance of each capacitor stage by adding capacitor trimmers, e.g., adding a digitally controlled capacitor array at each stage to compensate for capacitor mismatch. However, the digitally controlled capacitor array may need to be very large to cover the mismatching capacitance range in order to achieve the desired resolution in the charge distribution ADC.
Digital calibration techniques may use digital logic to calculate and store coefficients to correct each of the capacitor stages. However, digital techniques often utilize complex algorithms that require expensive and complex calibration logic. In addition, the calibration algorithms may have a long convergence time or may not be guaranteed to converge at all.